Verification Engineer

Verification Engineer
Company:

Ensilica India Private Limited


Verification Engineer

Details of the offer

Verification Engineer | Bangalore,India | ENS200420B

Job Reference: ENS200420B : Verification Engineer (Bangalore, India)

Role:

Good understanding of different methodologies, but particularly System Verilog and UVM. Faced with a new project, you will have the ability to quickly assimilate the verification challenge and help define an effective (and pragmatic) verification strategy.

Responsibilities:

Verification specialist working on projects as the verification engineer.
Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods.
As a verification engineer you would also be responsible for the development of a comprehensive verification strategy and plan, along with the architecting and development of the complete test environment.
Active participation in the verification community to drive the introduction of new and effective techniques to help solve the verification challenges faced in the projects.

Key Skills:
Bachelors Degree in Electronic Engineering or related discipline.
3 to 5 years of experience in UVM based verification
Strong knowledge in UVM and System Verilog in must
Strong protocol knowledge and expertise on USB2.0 serial interface
Deep understanding of USB2.0 Phy and interoperability/compliance issues
Working with Mentor QVIP based Verification environment or any other commercial VIP based verification environment.

Personal skills:

Excellent communication and interpersonal skills
Strong and effective presentation skills, able to operate at multiple levels including senior management
Self motivated
Take ownership of problems
Creative problem solving
Team player


Source: Timesjobs


Area:

Requirements

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