Principal Engineer - Ip Verification

Principal Engineer - Ip Verification


Principal Engineer - Ip Verification

Details of the offer

NXP Semiconductors N.V.enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 30,000 employees in more than 30 countries and posted revenue of $9.41 billion in 2018.
Key Responsibilities

Evaluate and deploy the evolving verification methodologies to handle increasingly complex IP/SubSystem designs within aggressive, market-driven schedules.
Own and ensure quality adherence during all stages of the project cycle. Ability to carry out a thorough analysis of existing processes, recommend and implement process improvements to ensure ‘Zero Defect’ IPs/SubSystems.
Building and Influencing technological innovations for self and in team environment.
Hands on and ability to work well as part of a team both locally, and with remote or multi-site teams.

Key Skills
Self starter with 10+ years of experience on IP / Sub-system verification on multimillion Gate and complex Design with multiple clocks with minimal supervision
Testbench and Testplan development to ensure thorough functional verification, and performance aspects of the IP along with Features traceability.
Experience in microcontroller architecture working with ARM cores, protocols like AHB/AMBA, AXI, Memory (Flash, SRAM,DDR) and memory controllers
Experience in domains like automotive Graphics / Vision accelerators, Slow and High Speed Serial IP controllers, Networking protocols like Ethernet, would be an added advantage
Must have experience and strong working knowledge of HVLs like (UVM/SV/C++), HDLs (Verilog/VHDL), PLI/DPI, simulators (NCSim/VCS/ModelSim/Questa).
Must have experience in end to end IP verification project cycle, including Testbench Strategies, TB development, simulation debugs.
Good Exposure to formal verification methodology, assertions/SVA, functional coverage, gate level simulations, verification planner and regression management.
Strong ability to drive verification methodologies is a highly desired for 10+ yrs candidates.
Exposure to pre silicon validation/emulation is an added advantage.

Source: Neuvoo3_Ppc


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