Lead Solutions Engineer

Lead Solutions Engineer
Company:

Cadence Design Systems, Inc


Lead Solutions Engineer

Details of the offer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description for R&D Solutions Role:
The Physical Verification R&D Solutions Software Engineering role is a multi-faceted position encapsulating a mix of expert-level physical verification methodology development, software performance / accuracy analysis, and optimization. R&D Solutions engineers collaborate with a large team of EDA professionals across multiple cultures to create and deliver best in class next generation software for physical IC application. The R&D solutions engineering role bridges software architecture development and end-user software deployment by designing, prototyping, and profiling methodologies to enable next-generation physical verification solutions with superior performance and usability. R&D Solutions engineers also provide methodology and flow guidance to engine developers across multiple physical verification subdomains, to ensure that code development satisfies the requirements for successful semiconductor design flow deployment. On a continuous basis R&D Solutions engineers deploy their mastery of physical verification DRC / LVS / fill applications, as well as physical implementation methodologies, to guide the accuracy, performance and functionality enhancements within the Cadence physical verification suite of products.
Desired Skills and Experience (with different levels of experience):
Intermediate Role in R&D Solutions
Experience in software development, product engineering or CAD flow development for DRC, LVS, Fill or DFM.
Must be a fast learner and must demonstrate strong aptitude for out-of-the-box thinking and problem solving.
Python language development experience in a large project is a plus, as is an experience in deck development for DRC or LVS (16nm or below).
Experience in physical signoff methodologies within the Physical implementation environment (DRC closure, chip assembly and finishing) would be an added advantage.
We’re doing work that matters. Help us solve what others can’t.


Source: Neuvoo3_Ppc


Area:

  • IT - Information Technology / Programmer

Requirements