At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Position RequirementsM.S. or BTech Electrical/Computer Engineering (or similar degree)Exp 5+ yearsExperience on cadence tools Experience in SOC design implementation, from RTL to final GDS. Static timing closure experience Experience with industry standard DFT flows and methodologies.Experience using advanced mixed signal verification, and system simulation tools.Exposure to all major IC implementation, design, and verification tools.Exposure to PCIe Controller Design , Functional Verification and Silicon Bring-up/Testing.Strong debug and problem-solving skillsAbility to clearly communicate technical challenges. Willing to travel to customer sites worldwideKnowledge of SOC platformsStrong communications skillsWorking with global (US, west coast and each coast) teams, which work in different time-zonesOverseas Travel
Position Description (what the role does)Main technical interface for customer pre and post silicon SOC.Primary technical contact for customer SOC and system integration questions.Support customer Pre-post silicon SOC teams from initial DDR integration and bring-up.Assist customer with GLS and timing closure.Work closely with DDR team and Field Application EngineersUpdate DDR teams with the latest customer feedback and competitive analysis.Drive and support Customer silicon evaluationsWork closely with Physical design team and RTL team to understand chip architecture, hierarchy.Perform gate level simulation and RTL simulation to verify functionality.
We’re doing work that matters. Help us solve what others can’t.